Sunday, October 30, 2011

Mentor Graphics Careers | Field Applications Engineer Design For Test \ 50372906 Vacancy

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Field Applications Engineer Design For Test \ 50372906
Job ID: 50372906E
Location: Bangalore, India

Responsible for Field Application Engineer (FAE) activities in the Design for Test (DFT) Domain From a technical stand-point, understanding customer needs on DFT, involve and work with their projects for using right methodologies and Mentor Graphics tools for successful project completion
 Involve and drive the Tool evaluation/benchmark; Technical product presentations; Methodology review; Tool deployment and adoption; Provide support to customers during critical Project implementation phases.
 Work with Technical Account manager and World Wide account teams for forming strategies and successfully driving Mentor Graphics tools inside customer projects to enable business success for Mentor Graphics
 Identify and work with potential new groups at customer sites, develop these groups technically for business engagement by way of introduction of new technologies and taking the success at other groups, drive competitive replacement engagement from a technical stand-point.
 Front end Mentor Engagements with customers, and Develop relationships with customer and be a trusted technical advisor to customers.
 Work with customer support division of Mentor graphics for issue resolution with the help of customer support engineer


 Educational qualifications :
o Required BE/B.Tech in Electronics & Communications Engineering (E&C), or Electrical and Electronics Engineering (EEE)
o Desired ME/M.Tech in VLSI or Microelectronics

 Work Experience:
o 5-8 years relevant experience in the Synthesis/DFT VLSI domain

 Technical skills :
o Should have served roles like Applications Engineer, Synthesis/Scan/DFT implementation Engineer handling medium to high complexity ASICs
o Work experience in handling test architectures for ASIC, test planning, scan architectures, fault modelling, fault/test coverage/analysis, Test diagnosis, Automatic Test Pattern Generation(ATPG) /Compression, ATPG simulation/debugging, AT-speed testing
o Work experience in handling Built in Self Test (BIST) techniques for memories and Logic (Memory BIST & Logic BIST), understanding of various Memory test algorithms
o Experience with Memory compilers, exposure to Memory repair solutions, understanding of verilog and ATPG library models,
o Understanding and handling Synopsys Design Constraints (SDC) and Static Timing Analysis (STA)
o Strong working knowledge in EDA tools like Mentor Graphics’ Fastscan, TestKompress, MBISTArchitect, DFTAdvisor, Synopsys DFT Compiler, Tetramax, DFTmax, Logic Vision’s BIST tools and other EDA tools in the related domain
o Scripting skills in TCL/TK/Perl would be desired
o Foundry exposure to ASIC testing and any experience with ATPG testers, Exposure to Analog DFT, testing special structures like PLLs, SERDES etc., would be an added advantage

 General/soft skills :
o Work effectively with sales, marketing, and R&D
o Ability to work autonomously
o Strong verbal and written communication skills; good presentation skills
o Excellent organizational and time management skills
o Build and foster relationships with customer and peers with a positive attitude to win business success
o Willingness for technical sales,
o Should be a good team player

For More Information and apply online visit : Mentor Graphics Careers or
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