Sunday, October 30, 2011

Mentor Graphics Careers | Lead Field Applications Engineer Functional Verification Vacancy

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Lead Field Applications Engineer Functional Verification \ 50375961
Job ID: 50375961E
Location: Bangalore, India

• Responsible for Field Application Engineering (FAE) activities in the Functional Verification (FV) Domain of VLSI systems• From a technical stand-point, understanding customer needs on FV, involve and work with their projects for using right methodologies and Mentor Graphics tools for successful project completion
• Involve and drive the Tool evaluation/benchmark; Technical product presentations; Methodology review; Tool deployment and adoption; drive competitive replacements, Provide support to customers during critical Project implementation phases.
• Involve in the Architectural review of projects, do code reviews, Conduct Verification assessment reviews, to arrive at a right and efficient verification platform for given customer environment.
• Work with Technical Account manager and World Wide account teams for forming strategies and successfully driving Mentor Graphics tools inside customer projects to enable business success for Mentor Graphics


• Should have served roles like Applications Engineer, Design/Verification engineer, Project lead handling medium to high complexity ASICs
• Work experience in planning, architecting and implementing verification needs
o Simulation using traditional methods like directed tests and advanced verification methods like constrained random testing and coverage driven verification methods.
o Register Transfer Level (RTL) and gate level design and verification
o Protocol knowledge and verification of one or more of AMBA (AHB, APB, AXI, APB3 and AXI-LP); AXI; Ethernet ; SPI ; HDMI ; USB,OTG, PCI, DDR etc.,
o Assertions – planning, implementation, verification and debug
o Code and functional Coverage & gate level simulations and debug
o Low power verification techniques using UPF or CPF
o Methodology : Verification of medium to complex SOCs using one or more of the verification methodologies like AVM,UVM, VMM, eRM and exposure to UVM. Strong hold on one or more of these methodologies is a must.
o Exposure to Clock Domain Crossing Analysis and Property checking methods would be an added advantage
• Strong working knowledge in EDA tools like Mentor Graphics’ Modelsim, Questa verification platform and/or Synopsys VCS, Vera, and/or Cadence NC-sim, Incisive verification platform, Specman
• Strong hold on VHDL/Verilog & System Verilog, and desirable ‘e’, Vera, PSL, SystemC knowledge.
• Required BE/B.Tech in Electronics & Communications Engineering (E&C), or Electrical and Electronics Engineering (EEE)
• Desired ME/M.Tech in VLSI or Microelectronics

For More Information and apply online visit : Mentor Graphics Careers or
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