Sunday, October 30, 2011

Mentor Graphics Careers | Senior Member Technical Staff \ 50379325 Vacancy

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Senior Member Technical Staff \ 50379325
Job ID: 50379325E
Location: Noida, India

Be an integral part of a team that is developing verification IPs such as PCIe, USB3, 100 Gigabit Ethernet and AMBA bus protocols for use with Questa RTL simulation. Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques.
You will specify, implement, test, and manage regression tests of these IPs for a wide range of end user applications. You will interact with TMEs and CSDs or directly with customers to resolve customer issues.


Job Requirements:
•Solid Verilog HDL RTL knowledge
• Solid RTL simulation and test bench experience
• Intimate knowledge of one or more standard bus protocols
• Solid engineering
• B.Tech/M.Tech in electrical engineering or related field
• 1-3 years of experience in verification engineering

Desired Requirements:
• Experience with cycle-based simulation and constrained-random simulation
• Experience with System Verilog or System C
• Knowledge of assertion languages such as SVA, PSL
• Experience with Formal Property Verification tools

Other Requirements:
Bus Protocol know how with SV, OVM, UVM, VMM, Specman knowhow etc.

For More Information and apply online visit : Mentor Graphics Careers or
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