Tuesday, November 1, 2011

Senior Asic / Dft Logic Design Lead Vacancy | NVIDIA Careers



SENIOR ASIC / DFT LOGIC DESIGN LEAD

Job ID 1440695
Location US, CA, Santa Clara

Description
SENIOR ASIC / DFT LOGIC DESIGN LEAD #1440695

As a DFT Logic Design Lead at NVIDIA, you'll be responsible for designing key DFT logic modules to be used on various NVIDIA products. This includes test mode controllers, IO test modules etc. You will need to work closely with design team on defining DFT solution, designing, verification, chip integration and bring-up. In addition you will be responsible for test pattern generation and bring-up and characterization.

MINIMUM REQUIREMENTS:
- BSEE required, MSEE preferred.
- 4 to 7 years of experience in DFT / design field.
- Understanding of Characterization of IO a plus.
- Extensive knowledge of JTAG and ieee1149.x standards.
- Strong logic Design and verification back ground with experience in STA.
- Must possess a working knowledge of DFT including scan, BIST.
- The candidate should be familiar with ASIC/Logic design flow including Verilog coding, verification, RTL/full chip simulation, timing closure, and ECO.
- General user support and documentation.
- Programming in Perl, TCL and C++ is a plus.
- Good communication skills.

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