Tuesday, November 1, 2011

Sr. Physical Design Engineer Vacancy | NVIDIA Careers



SR. PHYSICAL DESIGN ENGINEER

Job ID 1430764
Location US, CA, Santa Clara

Description
SENIOR PHYSICAL DESIGN ENGINEER #1430764

RESPONSIBILITIES:
- Responsible for the development of the physical design methodologies and flow automation for large and high speed semicustom chips using deep submicron processes (<=28nm).
- This includes evaluating and helping improve third party tools, developing internal tools and solutions, and supporting the physical design implementation team.

MINIMUM REQUIREMENTS:
- BSEE or BSCS
- 5+ years of experience in large VLSI physical design implementation and automation and methodology.
- Prior experience in timing closure, CTS, power distribution and analysis, power efficiency, RC extraction and correlation, xtalk analysis, signal EM, place and route, DRC/LVS and tapeout issues.
- Working knowledge of deep sub-micron issues.
- Should be a power user of P&R and timing analysis CAD tools such as Magma Talus (or Blast), Synopsys ICC (or DC/PT/STAR-RC/Astro/PC), Cadence SOCE, Mentor Graphics Pinnacle/Olympus or Atoptech.
- Proficiency using Perl, TCL, Make scripting.
- Knowledge / Proficiency of C/C++ or any other software language is a plus.
- Experience at 40nm, 28nm and 20nm process node is a plus.
- Circuit level comprehension of time critical paths and Spice experience are a plus.

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